A lockfree shared memory design for high-throughput multicore packet traffic capture
Author:
Affiliation:
1. Department of Artificial Intelligence, Computer Science and Systems Engineering; Kyushu Institute of Technology; Iizuka 820-8502 Japan
Publisher
Wiley
Subject
Computer Networks and Communications,Computer Science Applications
Link
http://onlinelibrary.wiley.com/wol1/doi/10.1002/nem.1866/fullpdf
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3. Chen R Chen H Zang B Tiled-MapReduce: optimizing resource usages of data-parallel applications on multicore with tiling 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) 2010 523 534
4. Machdi I Amagasa T Kitagawa H Executing parallel TwigStack algorithm on a multi-core system 11th International Conference on Information Integration and Web-based Applications and Services 2009 176 184
5. Parallel algorithm for integer sorting with multi-core processors;Stoichev;Information Technologies and Control,2009
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