Setting‐zero analysis for multistage amplifier design

Abstract

SummaryA setting‐zero analysis method is presented to facilitate the prediction of zeros in multistage amplifiers. The main objective of this method is to simplify the analysis process of such amplifiers while improving the overall performance, and the feasibility is confirmed by various examples presented in this paper. By proposing a single‐capacitor cascode Miller compensation three‐stage amplifier using setting‐zero analysis, this paper has theoretically verified that the addition of a grounding second‐stage compensation capacitor is unnecessary. Measurement results show that this amplifier consumes a current of 38 μA at a 1.2 V supply voltage, with a 103 dB open‐loop gain. When driving a 1 nF load capacitor, this design achieves 1.88 MHz gain bandwidth and 73° phase margin, with a 3.33 V/μs average slew rate and an average 1% settling time of 0.40 μs under the unity‐gain configuration.