1. Forward Body Biasing Techniques for Low Power Null Convention Logic in SOI;2024 Tenth International Conference on Communications and Electronics (ICCE);2024-07-31
2. Specific Investigations Concerning the Improveable Multiplier Architecture of High-Speed and Area-Efficient Adders;International Journal of Advanced Research in Science, Communication and Technology;2024-07-14
3. Self-Timed Counter Synthesis;2024 International Conference on Industrial Engineering, Applications and Manufacturing (ICIEAM);2024-05-20
4. QDI Binary Comparator Networks and their Application in Combinational Logic;2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS);2024-04-03
5. Self-Timed Counter Implementation Basis;2024 International Russian Smart Industry Conference (SmartIndustryCon);2024-03-25