Device and circuit level performance assessments of gate engineered Ge/GaAs heterojunction doping less TFET

Abstract

AbstractRecently, the doping‐less tunnel FET has gained popularity due to its lower process complexity than conventional TFETs with heavily doped source and drain regions. In this literature, we have introduced a symmetric gate Ge/GaAs heterojunction doping‐less TFET(SG HJ DL TFET) using 4.6 eV work function for both the top gate and bottom gate and an asymmetric gate Ge/GaAs heterojunction doping‐less TFET (AG HJ DL TFET) using 3.9 eV work function as top gate and 4.6 eV work function as a bottom gate. A comparative study has been performed between these two devices. The back gate misalignment engineering in the AG HJ DL TFET induces higher charge plasma near the source‐channel junction which will enhance the drain current. Due to a larger drain current, an improved ratio (11.8 times), and steeper SS (37%) are achieved in optimized AG HJ DL TFET than SG HJ DL TFET. Furthermore, the Analog/Radio Frequency and linearity performance parameters have been examined, and a significant improvement is noticed in the optimized AG HJ DL TFET. The impact of different interface trap charges (ITCs) on device performances is also investigated and it is found that AG HJ DL TFET shows more immunity to ITCs than SG HJ DL TFET. Finally, the Verilog‐A‐based model has been developed for the AG HJ DL TFET to utilize its circuit‐level behavior. The optimized device‐based Common Source amplifier (CS amplifier) has been simulated in the Cadence Virtuoso tool. The AG HJ DL TFET‐based CS amplifier offers a 6.83% improvement in voltage gain over the other reported work.