Energy‐efficient system‐on‐chip reconfigurable architecture design for sum of absolute difference computation in motion estimation process of H.265/HEVC video encoding-Reference-Cited by-同舟云学术

Energy‐efficient system‐on‐chip reconfigurable architecture design for sum of absolute difference computation in motion estimation process of H.265/HEVC video encoding

Published:2019-07-31 Issue: Volume: Page:
ISSN:1532-0626
Container-title:Concurrency and Computation: Practice and Experience
language:en
Short-container-title:Concurrency Computat Pract Exper

Author:

Chandran K.R. Sarath¹^ORCID,Chandramani Premanand Venkatesh²

Affiliation:

1. Department of Computer Science and EngineeringSri Sivasubramaniya Nadar College of Engineering Chennai India

2. Department of Electronics and Communication EngineeringSri Sivasubramaniya Nadar College of Engineering Chennai India

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/cpe.5461

Reference18 articles.

1. Overview of the high efficiency video coding (HEVC) standard;Sullivan GJ;IEEE Trans Circuits Syst Video Technol,2012

2. HM Reference Software.https://hevc.hhi.fraunhofer.de/svn/svn_HEVCSoftware/

3. A data‐interlacing architecture with two‐dimensional data‐reuse for full‐search block‐matching algorithm;Lai Y‐K;IEEE Trans Circuits Syst Video Technol,1998

4. Reconfigurable hardware implementation of an improved parallel architecture for MPEG‐4 motion estimation in Mobile applications;Gao R;IEEE Trans Consum Electron,2003

5. A memory efficient and highly parallel architecture for variable block size integer motion estimation in H.264/AVC;Kao C‐Y;IEEE Trans VLSI Syst,2010

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