Tail queues: A multi‐threaded matching architecture

Author:

Dosanjh Matthew G.F.12ORCID,Grant Ryan E.12,Schonbein Whit12,Bridges Patrick G.2

Affiliation:

1. Center for Computing ResearchSandia National Laboratories Albuquerque New Mexico

2. Department of Computer ScienceUniversity of New Mexico Albuquerque New Mexico

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Reference40 articles.

1. Los Alamos National Laboratory.The Trinity Advanced Technology System.http://www.lanl.gov/projects/trinity/. Accessed March 19 2015.

2. NERSC.NERSC‐8 System: Cori.https://www.nersc.gov/users/computational-systems/cori/. Accessed March 19 2015.

3. An evaluation of MPI message rate on hybrid-core processors

4. MPI Forum.MPI: A Message‐Passing Interface Standard. Version 3.1. June 4th 2015.

5. KlenkB FröningH EberleH DennisonL.Relaxations for high‐performance message passing on massively parallel SIMT processors. Paper presented at: 2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS);2017;Orlando FL.

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