A global delay model for domino cmos circuits with application to transistor sizing-Reference-Cited by-同舟云学术

A global delay model for domino cmos circuits with application to transistor sizing

Published:1990-05 Issue:3 Volume:18 Page:289-306
ISSN:0098-9886
Container-title:International Journal of Circuit Theory and Applications
language:en
Short-container-title:Int. J. Circ. Theor. Appl.

Author:

Kang S. M.,Chen H. Y.

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference10 articles.

1. High-speed compact circuits with CMOS

2. , and , ‘A CMOS 32-bit single chip microprocessor’, 1981 ISSCC Digest Tech Papers, IEEE Press, New York, pp. 230–231, Feb. 1981.

3. FFT scaling in Domino CMOS gates

4. and , ‘Performance optimization for domino CMOS circuit modules’, Proc. Int. Conf. on Computer Design (ICCD), IEEE Press, Port Chester, New York, October 1987, pp. 522–525.

5. Handbook of Mathematical Sciences, Chemical Rubber Company, 1975, pp. 40–41.

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