Affiliation:
1. Warsaw University of Technology, Institute of Telecommunications, Nowowiejska 15/19, Warsaw 00-665, Poland
Abstract
An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in this
paper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representation
of the function by a set of r-partitions over the set of minterms. Two different decomposition strategies, namely serial and
parallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completely
or incompletely specified, single- or multiple-output functions and is suitable for different types of FPGAs including
XILINX, ACTEL and ALGOTRONIX devices. The results of the benchmark experiments presented in the paper show that,
in several cases, our method produces circuits of significantly reduced complexity compared to the solutions reported in the literature.
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture
Cited by
33 articles.
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