Author:
Długosz Rafał,Iniewski K.
Abstract
A novel 8-bit current mode interleaved successive approximation (SAR) analog-digital
converter (ADC) has been proposed. The proposed converter architecture is very
flexible. Using two control DC voltages and one reference current, the converter can
be tuned to work with different sampling rates, number of bits of resolution, and power
consumption levels. Due to its very low-power consumption and flexibility, the converter is
particularly suitable for application in wireless sensor networks. Compared to other solutions
presented in the literature, the proposed converter achieves very high figure of merit (FOM)
value due to numerous low-power circuit innovations utilized in its design. The circuit has been
implemented in CMOS 0.18 μm technology. Minimum energy consumption has been found to be in
a 25–250 kS/s range (for clock sampling frequency in a 200 kHz--2 MHz
range) for a single SAR section with the corresponding power dissipation varying
from 220 nW to 560 nW for 0.55 V power supply.
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture
Cited by
16 articles.
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