APRON: A Cellular Processor Array Simulation and Hardware Design Tool
Author:
Publisher
Springer Science and Business Media LLC
Link
http://link.springer.com/content/pdf/10.1155/2009/751687.pdf
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1. Design of a Massively Parallel Processor
2. ACE16k: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs
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