Development and Implementation of a Low-Cost Test Solution for High-Precision ADC Chips Based on Intelligent Sensor Networks

Abstract

Analog-to-digital converters (ADCs) are moving toward high speed and high resolution for low-cost testing. Based on the theory of intelligent sensor network, this paper designs a low-cost test solution for high-precision ADC chips, which solves the problems related to signal integrity. It mainly includes the following: designing an appropriate circuit connection scheme, planning an appropriate PCB stack-up structure, formulating detailed layout and wiring constraints, etc., and building a high-speed ADC test platform to obtain static and dynamic performance; based on the existing instruments in the laboratory, the effects of different signal sources, different input powers, and the presence or absence of filters on the dynamic performance of high-speed ADCs are studied. In the simulation process, the HyperLynx simulation platform is used to design and simulate the signal integrity of the high-speed acquisition board. Combined with the relevant theoretical knowledge of the signal integrity of high-speed digital circuits, the signal integrity analysis and simulation of the ADC module circuit and the DDR3 high-speed memory circuit are carried out, respectively. The results show that, taking the histogram method as a reference, when the optimal 30 windows are selected, the integral nonlinearity (INL) error of the proposed method is 0.12 LSB, the highest sampling frequency is up to 5GSps, and 61440 sampling points are required. The time is reduced by about 30% compared with the excitation error identification and removal (SEIR) method, which effectively improves the low-cost test effect of the ADC chip.