Distributed Fault Simulation Algorithms on Parallel Virtual Machine
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Published:2001-01-01
Issue:1
Volume:12
Page:81-99
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ISSN:1065-514X
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Container-title:VLSI Design
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language:en
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Short-container-title:VLSI Design
Author:
Ravikumar C. P.1,
Jain Vikas1,
Dod Anurag1
Affiliation:
1. Department of Electrical Engineering, Indian Institute of Technology, New Delhi 110016, India
Abstract
In this paper, we describe distributed algorithms for combinational fault simulation
assuming the classical stuck-at fault model. Our algorithms have been implemented
on a network of Sun workstations under the Parallel Virtual Machine (PVM) environment.
Two techniques are used for subdividing work among processors – test set
partition and fault set partition. The sequential algorithm for fault simulation, used on
individual nodes of the network, is based on a novel path compression technique
proposed in this paper. We describe experimental results on a number of ISCAS′85
benchmark circuits.
Publisher
Hindawi Limited
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture