Affiliation:
1. School of Computer Science, Carleton University, Ottawa K1S 5B6, Canada
Abstract
A common technique widely used to achieve fault tolerance in systolic arrays consists in
incorporating in the array additional processing elements (PEs) and extra bypass links.
Given a sufficient number of PEs and a large enough set of bypass links, it might seem
that the array can easily tolerate a large number of faults provided they do not occur in
consecutive locations. It is not always the case as shown in this paper. In fact, certain
fault patterns exist and may occur which would prevent any kind of restructuring of the
aray, thus making the structure unusable. For a given set of bypass links from each PE
in the array, it is possible to identify such fault patterns which will prevent any
reconfiguration. In this paper, we identify the class of fault patterns that are
catastrophic for linear systolic arrays, examine their characteristics, and describe a
method for constructing such fault patterns.
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture