Affiliation:
1. Courant Institute of Mathematical Sciences, New York University, USA
Abstract
We present the design for the two VLSI components used in a processor-to-memory interconnection network for
a shared memory system. These components allow the combining of requests that are destined to the same memory
location. The design contains both semi-systolic queues and an associative “wait buffer.” Transition equations and
schematics of the critical pieces of the design are included.
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture
Cited by
6 articles.
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