Affiliation:
1. Department of Electrical and Electronic Engineering, Public University of Navarra, Arrosadía s/n., Pamplona E-31006, Spain
Abstract
A general framework for designing current-mode CMOS analog multiplier/divider
circuits based on the cascade connection of a geometric-mean circuit and a squarer/divider is presented. It is shown how both building blocks can be readily obtained from
a generic second-order MOS translinear loop. Various implementations are proposed,
featuring simplicity, favorable precision and wide dynamic range. They can be successfully
employed in a wide range of analog VLSI processing tasks. Experimental
results of two versions, based on stacked and folded MOS-translinear loops and fabricated
in a 2.4-μm CMOS process, are provided in order to verify the correctness of
the proposed approach.
Funder
Comisión Interministerial de Ciencia y Tecnología
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture
Cited by
12 articles.
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