Efficient Low Power/Low Swing Bus Design Architectures

Abstract

Novel low-power circuits based on low swing voltage technique, in the internal nodes of bus architectures, are proposed. Different classes of driver/receiver and repeater circuits are presented. They are implemented on conventional CMOS technology. The proposed technique is based on inserting a variable number of MOSFET transistors in the driver circuits, causing variable low swing voltage levels in the output of the driver circuits. In order to re-pull up the low swing voltage to full swing, innovated high-speed, crosscoupled latch voltage receiver circuits are proposed. In applications having high load capacitance due to long interconnections, novel repeater circuits, based also on low swing voltage technique, are introduced. The difference between the values of threshold voltage of the nMOS transistor and the pMOS transistors is exploited to decrease the power dissipation. The effect of the proposed technique in noise margins is also analysed.