Optimal Design of Voltage Reference Circuit and Ring Oscillator Circuit Using Multiobjective Differential Evolution Algorithm

Author:

Dash Sandeep K.1ORCID,De Bishnu Prasad1ORCID,Samanta Pravin K.1ORCID,Appasani Bhargav1ORCID,Kar Rajib2ORCID,Mandal Durbadal2ORCID,Bizon Nicu345ORCID

Affiliation:

1. School of Electronics Engineering, KIIT University, Bhubaneswar 751024, Odisha, India

2. Department of Electronics & Communication Engineering, NIT Durgapur, Durgapur, West Bengal 713209, India

3. Faculty of Electronics, Communication and Computers, University of Pitesti, Pitesti 110040, Romania

4. University Politehnica of Bucharest, Splaiul Independentei Street No. 313, Bucharest 060042, Romania

5. ICSI Energy, National Research and Development Institute for Cryogenic and Isotopic Technologies, 240050 Ramnicu Valcea, Romania

Abstract

This paper deals with the optimal design of different VLSI circuits, namely, the CMOS voltage reference circuit and the CMOS ring oscillator (RO). The optimization technique used here is the multiobjective differential evolution algorithm (MDEA). All the circuits are designed for 90 nm technology. The main objective of the CMOS voltage reference circuit is to minimize the voltage variation at the output. The targeted value of the reference voltage is 550 mV. A CMOS ring oscillator (RO) is designed depending on the performance parameters such as power consumption and phase noise. The optimal transistor sizing of each circuit is obtained from MDEA. Each circuit is implemented in SPICE by taking the optimal dimensions of the transistors, and the performance parameters are achieved. The designed voltage reference circuit achieves a reference voltage of 550 mV with 600 nW power dissipation. The reference voltage variation of 8.18% is observed due to temperature variation from −40°C to + 125°C. The MDEA-based optimal design of RO oscillates at 2.001 GHz frequency, has a phase noise of −87 dBc/Hz at 1 MHz offset frequency, and consumes 71 μW power. This work mainly aims to optimize the MOS transistors’ sizes using MDEA for better circuit performance parameters. SPICE simulation has been carried out by using the optimal values of MOS transistor sizes to exhibit the performance parameters of the circuit. Simulation results establish that design specifications are closely met. SPICE results show that MDEA is a better technique for the optimal design of the above-mentioned VLSI circuits.

Publisher

Hindawi Limited

Subject

Electrical and Electronic Engineering,General Computer Science,Signal Processing

Reference40 articles.

1. An optimized device sizing of analog circuits using genetic algorithm;P. P. Kumar;European Journal of Scientific Research,2012

2. Automatic synthesis of analog integrated circuits using genetic algorithms and electrical simulations;L. C. Severo;Proc. 24th South Symp,2009

3. Comparative study of ant colony and genetic algorithms for VLSI circuit partitioning;S. S. Gill;World Acad. Sci.Eng. Technol.,2009

4. A Parallel genetic algorithm for floorplan area optimization;M. Tang

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