A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

Author:

Pola Ariel L.1,Cousseau Juan E.2,Agazzi Oscar E.3,Hueda Mario R.1

Affiliation:

1. Laboratorio de Comunicaciones Digitales, Universidad Nacional de Córdoba, CONICET, Avenida Vélez Sarsfield 1611, Córdoba X5016GCA, Argentina

2. Universidad Nacional del Sur, IIIE, CONICET, Avenida Alem 1253, Bahía Blanca B8000CPB, Argentina

3. ClariPhy Communications, Inc., 7585 Irvine Center Drive, Suite 100, Irvine, CA 92618, USA

Abstract

This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers in the presence of highly dispersive channels. This decision-aided equalizer technique has been recently proposed for multigigabit communication receivers, where the use of parallel processing is mandatory. Well-known parallel architectures for the typical decision feedback equalizer (DFE) have a complexity that grows exponentially with the channel memory. Instead, the new DFFE avoids that exponential increase in complexity by using tentative decisions to cancel iteratively the intersymbol interference (ISI). Here, we demostrate that the DFFE not only allows to obtain a similar performance to the typical DFE but it also reduces the compelxity in channels with large memory. Additionally, we propose a theoretical approximation for the error probability in each iteration. In fact, when the number of iteration increases, the error probability in the DFFE tends to approach the DFE. These benefits make the DFFE an excellent choice for the next generation of high-speed receivers.

Publisher

Hindawi Limited

Subject

Electrical and Electronic Engineering,General Computer Science,Signal Processing

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design Techniques for optimizing an Adaptive Decision Feedback Equalizer for 5G Communication;2024 International Conference on Knowledge Engineering and Communication Systems (ICKECS);2024-04-18

2. An Energy Efficient VLSI Architecture of Decision Feedback Equalizer for 5G Communication System;IEEE Journal on Emerging and Selected Topics in Circuits and Systems;2017-12

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