PCM-2R: Accelerating MLC PCM Writes via Data Reshaping and Remapping

Author:

Hong Feng1ORCID,Zhang Jianquan23ORCID,Qi Shigui4ORCID,Li Zheng5ORCID

Affiliation:

1. Institute of Electronics and Information Engineering, Hubei University of Science and Technology, Xianning, China

2. Institute of Engineering and Technology, Hubei University of Science and Technology, Xianning, China

3. Hubei Xiangcheng Intelligent Electromechanical Industry Technology Research Institute Co Ltd, Xianning, China

4. Henan University of Economics and Law, Zhengzhou, China

5. Huawei Technologies Co Ltd, Shenzhen, China

Abstract

Multilevel cell (MLC) phase change memory (PCM) shows great potential in terms of capacity and cost compared with single-level cell (SLC) PCM by storing multiple bits in one physical PCM cell. However, poor write performance is a huge challenge for MLC PCM. In general, write latency of MLC PCM is 10 to 100X longer compared with DRAM technology. Considerable write latency greatly degrades the overall system performance and restricts the application of MLC PCM. Actually, several chips compose a memory DIMM to match the wide interface of data bus. The data of a write request, i.e., a cache line block, are distributed to multiple PCM chips. As a result, the write service time is determined by the chips with the most data amount. Conventional PCM write schemes do not care for the modified-byte distribution among PCM chips and it just waits for the completion of the chip with the most amount of data. However, it is observed that (1) the conventional PCM write scheme suffers from unbalanced modified-byte distribution that some PCM chips bear too many modified bytes while some chips are kept idle for long times. (2) The modified-byte distribution shows some unique patterns that some bytes are changed more frequently compared with others. (3) MLC PCM shows significant asymmetry considering only MSB or LSB transitions. Based on these observations, in order to solve the poor write problem of PCM, this article presents a novel PCM write scheme called PCM-2R. The key ideas behind our proposed scheme are to reshape the data to evenly distribute the cache line blocks among all chips based on their modified-byte distribution pattern to avoid unbalanced distribution and then remap modified bytes to fast region after decoupling MLC PCM cells considering the state transition asymmetries. The evaluation results show that PCM-2R achieves 51% read latency reduction, 37% write latency reduction, 1.9X IPC improvement, 41% running time reduction, 2.2X throughout improvement, and 52% energy reduction compared with the baseline. Moreover, compared with the state-of-the-art write schemes, PCM-2R achieves 0.2X more IPC improvement and 0.2X throughout improvement.

Publisher

Hindawi Limited

Subject

Computer Networks and Communications,Computer Science Applications

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