An Improved Harmony Search Approach for Block Placement for VLSI Design Automation

Author:

Karimullah Shaik1ORCID,Vishnuvardhan D.1,Arif Muhammad2ORCID,Gunjan Vinit Kumar3,Shaik Fahimuddin4ORCID,Siddiquee Kazy Noor-e-alam5ORCID

Affiliation:

1. Department of Electronics and Communication Engineering, JNTUA Ananthapuramu, Andhra Pradesh, India

2. Department of Computer Science and Information Technology, University of Lahore, Pakistan

3. Department of Computer Science and Engineering, CMR Institute of Technology Hyderabad, India

4. Department of Electronics and Communication Engineering, Annamacharya Institute of Technology & Sciences, Rajampet, India

5. Department of Computer Science and Engineering, University of Science and Technology, Chittagong, Bangladesh

Abstract

The technology grows quickly in the area of the VLSI physical design; it is crucial to integrate the greater number of transistors and parts into a very small range. Before the placement is completed, the physical and technical positioning of the blocks in the chip area is planned, which is nothing but floor planning. In order to lessen the placement region in the physical layout, floor planning must be carried out effectively. This paper proposes a blended harmony search and particle swarm optimization (BHSPS) algorithm which is the deliberate blend of the harmony search (HS) algorithm, and the particle swarm optimization (PSO) algorithm is proposed to acquire the central goal of the VLSI placement strategy. The objective here is to lessen the field of plan. The MATLAB code for the blended harmony search and particle swarm optimization (BHSPS) algorithm is compiled, and investigations were carried out for better examination through the standard MCNC, i.e., North Carolina Microelectronics Center benchmark circuits.

Publisher

Hindawi Limited

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Information Systems

Reference19 articles.

1. Physical vs. physically-aware estimation flow: case study of design space exploration of adders;I. Ratkovi

2. KarimullahS.VishnuvardhanD.Experimental Analysis of Optimization Techniques for Placement and Routing in Asic Design2020Springer Nature Singapore Pte Ltd.ICDSMLA 2019, Lecture Notes in Electrical Engineering

3. Fast floorplanning with placement constraints;S. Pinge

4. Power, performanceand area optimization of I/O design;Iyengarand Lakhshmi Shrinivasn

5. Iterative analysis of optimization algorithms for placement and routing in Asic design;S. Karimullah,2020

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