A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node

Author:

Yin Jiayu1,Liao Wenli1,Chen Chengying1ORCID

Affiliation:

1. School of Opto-Electronic and Communication Engineering, Xiamen University of Technology, Xiamen 361024, China

Abstract

Combining with a static random-access memory (SRAM) and resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell is proposed in this study. With differential mode, a pair of 1T1R RRAM is added to 6T SRAM storage node. By optimizing the connection and layout scheme, the power consumption is reduced and the data stability is improved. The nvSRAM memory cell is realized with UMC CMOS 28 nm 1p9m process. When the power supply voltage is 0.9 V, the static noise/read/write margin is 0.35 V, 0.16 V, and 0.41 V, respectively. The data storage/restoration time is 0.21 ns and 0.18 ns, respectively, with an active area of 0.97 μm2.

Funder

Xiamen Youth Innovation Fund Project

Publisher

Hindawi Limited

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

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