Affiliation:
1. Department of Electronic Engineering, Feng Chia University, Taichung 40724, Taiwan
Abstract
A CMOS amplifier with differential input and output was designed for very high common-mode rejection ratio (CMRR) and low offset. This design was implemented by the 0.35 μm CMOS technology provided by TSMC. With three stages of amplification and by balanced self-bias, a voltage gain of 80 dB with a CMRR of 130 dB was achieved. The related input offset was as low as 0.6 μV. In addition, the bias circuits were designed to be less sensitive to the power supply. It was expected that the whole amplifier was then more independent of process variations. This fact was confirmed in this study by simulation. With the simulation results, it is promising to exhibit an amplifier with high performances for biomedical applications.
Funder
National Science Council (NSC), Republic of China
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture
Cited by
10 articles.
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