Affiliation:
1. Department of Electrical Engineering, National Tsing Hua University, Hsinchu 300, Taiwan
Abstract
We present in this paper an approach to designing partially strongly code-disjoint
(PSCD) CMOS circuits and checkers, considering transistor stuck-on faults in addition
to gate-level stuck-at faults. Our design-for-testability (DFT) technique requires only a
small number of extra transistors for monitoring abnormal static currents, coupled with
a simple clocking scheme, to detect the stuck-on faults concurrently. The DFT circuitry
not only can detect the faults in the functional circuit but also can detect or tolerate faults
in itself, making it a good candidate for checker design. Switch and circuit level
simulations were performed on a sample circuit, and a sample 4-out-of-8 code checker
chip using the proposed technique has been designed, fabricated, and tested, showing the
correctness of the method. Performance penalty is reduced by a novel BiCMOS checker
circuit.
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture