A Hardware-Efficient Programmable FIR Processor Using Input-Data and Tap Folding

Author:

Chen Oscal T.-C.,Chen Li-Hsun

Publisher

Springer Science and Business Media LLC

Reference17 articles.

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3. Chen L-H, Chen OT-C: A low-complexity and high-speed Booth-algorithm FIR architecture. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '01), May 2001, Sydney, NSW, Australia 4: 338-341.

4. Chen L-H, Chen OT-C: A hardware-efficient FIR architecture with input-data and tap folding. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '05), May 2005, Kobe, Japan 1: 544-547.

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Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design and verification of an ALU‐based universal FIR filter;COMPEL - The international journal for computation and mathematics in electrical and electronic engineering;2010-03-09

2. Power-Efficient and Low Latency Implementation of Programmable FIR filters Using Carry-Save Arithmetic;2007 14th IEEE International Conference on Electronics, Circuits and Systems;2007-12

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