Zener Zap Anti-Fuse Trim in VLSI Circuits

Author:

Comer Donald T.1

Affiliation:

1. Brigham Young University, Provo 84602, UT, USA

Abstract

This paper presents an overview of Zener zap anti-fuse trim as used to achieve improved accuracy in precision integrated circuits. Because this technology spans design and manufacturing, elements of design, layout, processing, and testing are included. The mechanism is defined and typical applications are discussed. Layout considerations of anti-fuse devices are summarized and complex trim networks and multiplexed control methods are presented. Both bipolar and CMOS process implementations are considered. The paper also contains a bibliography which includes U.S. patents, which make up a large part of the technical documentation of this technology.

Publisher

Hindawi Limited

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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2. Improved current filament control during Zener diode zapping;Microelectronics Reliability;2012-09

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4. Laser-Induced Resistance Fine Tuning of Integrated Polysilicon Thin-Film Resistors;IEEE Transactions on Electron Devices;2011-02

5. A precision architecture for high-speed amplifier applications;2009 52nd IEEE International Midwest Symposium on Circuits and Systems;2009-08

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