Fault Modeling and Testing for Analog Circuits in Complex Space Based on Supply Current and Output Voltage

Author:

Hu Hongzhi12,Tian Shulin1,Guo Qing2

Affiliation:

1. School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China

2. Guangxi Key Laboratory of Automatic Detecting Technology and Instrument, Guilin University of Electronic Technology, Guilin 541004, China

Abstract

This paper deals with the modeling of fault for analog circuits. A two-dimensional (2D) fault model is first proposed based on collaborative analysis of supply current and output voltage. This model is a family of circle loci on the complex plane, and it simplifies greatly the algorithms for test point selection and potential fault simulations, which are primary difficulties in fault diagnosis of analog circuits. Furthermore, in order to reduce the difficulty of fault location, an improved fault model in three-dimensional (3D) complex space is proposed, which achieves a far better fault detection ratio (FDR) against measurement error and parametric tolerance. To address the problem of fault masking in both 2D and 3D fault models, this paper proposes an effective design for testability (DFT) method. By adding redundant bypassing-components in the circuit under test (CUT), this method achieves excellent fault isolation ratio (FIR) in ambiguity group isolation. The efficacy of the proposed model and testing method is validated through experimental results provided in this paper.

Funder

National Natural Science Foundation of China

Publisher

Hindawi Limited

Subject

Applied Mathematics

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