Tutorial on VLSI Partitioning

Author:

Chen Sao-Jie1,Cheng Chung-Kuan2

Affiliation:

1. Dept. of Electrical Engineering, National Taiwan University, Taipei 10764, Taiwan

2. Dept. of Computer Science and Engineering, University of California, San Diego, La Jolla 92093-0114, CA, USA

Abstract

The tutorial introduces the partitioning with applications to VLSI circuit designs. The problem formulations include two-way, multiway, and multi-level partitioning, partitioning with replication, and performance driven partitioning. We depict the models of multiple pin nets for the partitioning processes. To derive the optimum solutions, we describe the branch and bound method and the dynamic programming method for a special case of circuits. We also explain several heuristics including the group migration algorithms, network flow approaches, programming methods, Lagrange multiplier methods, and clustering methods. We conclude the tutorial with research directions.

Publisher

Hindawi Limited

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. TBPart: An Effective Topological Order Balanced Hypergraph Partitioning Algorithm for VLSI Processor-based Hardware Emulation;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

2. Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

3. SALAH: Simulation-Assisted LAyout Hierarchy Construction;2021 22nd International Symposium on Quality Electronic Design (ISQED);2021-04-07

4. Depth-bounded Graph Partitioning Algorithm and Dual Clocking Method for Realization of Superconducting SFQ Circuits;ACM Journal on Emerging Technologies in Computing Systems;2021-01-31

5. Tree Structures and Algorithms for Physical Design;Proceedings of the 2018 International Symposium on Physical Design;2018-03-25

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