Supply Voltage Scaling for Energy Efficient FinFET Logic

Abstract

A number of ultra-low power applications that don't need high performance can gain power from running at the lowest supply voltage possible. Scaling the supply voltage is a useful technique for cutting the energy needed by digital circuitry. Based on Shannon's channel capacity theorem, the fundamental limit for supply voltage for planar CMOS circuits has been determined to be 36 mV. FinFET devices fit ultra-low voltage applications better than planar devices because of their nearly excellent sub-threshold properties. For the first time, the fundamental supply voltage limit for logic circuits using FinFETs has been defined in this work. It is discovered that this theoretical limit is considerably lower than the limit for planar CMOS devices. On this fundamental limit, the impact of temperature variations and device design characteristics is also investigated. Other logic gates, such as the NAND gate, are included in the analysis. To determine this fundamental limit for a FinFET device, a novel physics-based, semi-empirical current equation valid for supply voltage below 100 mV has been proposed. This is because the operation of a FinFET device in the ultra-low voltage domain differs significantly from that of its planar counterpart. A circuit designer values a current model like this because it makes calculations for back of the envelope calculations simple. The proposed model is then used to study the logic gates functioning in this regime.