A Study on Sensitivity of Some Switching Parameters of JLT to Structural Parameters
-
Published:2020-08-26
Issue:4
Volume:10
Page:433-446
-
ISSN:2210-6812
-
Container-title:Nanoscience & Nanotechnology-Asia
-
language:en
-
Short-container-title:NANOASIA
Author:
Ghosal Subhro1, Ganguly Madhabi2ORCID, Ghosh Debarati3
Affiliation:
1. Department of Electronic Science, APC College, Kolkata, India 2. Department of Electronics, West Bengal State University, Kolkata, India 3. Department of Basic Sciences and Humanities, RERF, Kolkata, India
Abstract
Background:
The stringent technological constraints imposed by the requirement of
ultra-sharp doping profiles associated with the sub-30 nm regime has led to the search for alternatives
to the conventional Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET). An
obvious alternative is a device whose architecture does not have any junctions in the sourcechannel-
drain path. One such device is the Junctionless transistor comprising of an isolated ultrathin
highly doped semiconductor layer whose volume is fully depleted in the OFF state and is
around flat- band in the ON state. Such a structure overcomes the stringent technological requirement
of an ultra-sharp grading profile required for nano-scale MOSFETs. For widespread application
in today’s high-speed circuits, a key factor would be its effectiveness as a switch.
Methods:
In this work we have studied the relative sensitivity of two such parameters namely the
ION/IOFF ratio and gate capacitance to variations in several structural parameters of the device
namely channel width, composition of the dielectric layer, material composition of the channel region
(i.e. Si vis-à-vis SiGe), doping concentration of the channel region and non-uniformity in the
doping profile.
Results:
The work demonstrates through device simulations that replacement of Si with Si-Ge
leads to an improvement in the performance.
Conclusion:
The most notable change has been observed by using a vertically graded doping profile
as opposed to the original proposed uniformly doped channel.
Publisher
Bentham Science Publishers Ltd.
Subject
General Engineering,General Materials Science
Reference44 articles.
1. International Technology Roadmap for Semiconductors (ITRS) . Available at: http://www.itrs.net 2. Skotnicki,T.; Merckel,G.; Pedron, T. The. tage-doping trans-formation: A new approach to the modeling of MOSFET short-channel effects. IEEE Electron Device Lett. 1988,9,109. [http://dx.doi.org/10.1109/55.2058] 3. Barraud,S.; Berthomé, M.; Coquand,R.; Cassé, M.; Ernst,T.; Samson, M-P.; Perreau,P.; Bourdelle, K.K.; Faynot,O.; Poiroux, T. Scaling of trigate junctionless nanowire MOSFET with gate length down to 13 nm. IEEE Electron Device Lett. 2012,33(9),1225-1227. [http://dx.doi.org/10.1109/LED.2012.2203091] 4. Colinge, J-P.; Lee, C-W.; Afzalian,A.; Akhavan, N.D.; Yan,R.; Ferain,I.; Razavi,P.; O’Neill,B.; Blake,A.; White,M.; Kelleher, A-M.; McCarthy,B.; Murphy, R. Nanowire transistors without junctions. Nat. Nanotechnol. 2010,5(3),225-229. [http://dx.doi.org/10.1038/nnano.2010.15] [PMID: 20173755] 5. Colinge, J.P.; Lee, C.W.N. Akhavan, D.R. Yan,I.; Ferain,P.; Razavi,A.; Yu, R. Junctionless Transistors: Physics and Proper-ties, Springer-Verlag: Berlin, Heidelberg. 2011
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
|
|