Design Techniques for Power-Gated Nanoscale Low Power Circuits

Abstract

Background: With the shrinking device-sizes in the present day world, the leakage power of the devices has also been increased significantly. Several techniques have been proposed to minimize the leakage power. However, the techniques have certain limitations, such as noise, delay or area of the chip. We have also proposed a leakage minimization technique which also minimizes the noise in the circuit. Objective: In this paper, we propose noise minimization circuit techniques for the distributed sleep transistor network in power-gated Multi-threshold CMOS circuits. The objective is to minimize leakage power as well as the noise associated with digital power-gated circuits. Methods: The proposed technique has been verified through simulations using the Cadence virtuoso tool. The proposed technique has been applied to a 16-bit adder circuit in 45 nm MTCMOS technology. Results: The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve 99%, 64.8% and 62.07% reduction in noise as compared to the All-ON, variable-width and variable gate-voltage techniques, respectively. The behavior of the circuit techniques has also been analyzed at higher temperatures. It has been shown through simulations that the proposed techniques effectively minimize noise at higher temperatures i.e. 75°C and 115°C. The proposed techniques also minimize leakage power and the on-time delay significantly. A layout of the section of the proposed circuit has also been drawn which occupies the chip area of 2.37 µm2. Conclusion: The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve a significant reduction in the noise as well as delay. In this paper, we propose leakage minimization techniques for the distributed sleep transistor network. The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve a significant reduction in noise as well as delay. The technique also reduces the leakage power significantly.