Parametric Analysis of Indium Gallium Arsenide Wafer-based thin body (5 nm) Double-Gate MOSFETs for Hybrid RF Applications

Abstract

Introduction: The electrical behavior of a high-performance Indium Gallium Arsenide (InGaAs) wafer-based n-type Double-Gate (DG) MOSFET with a gate length (LG1= LG2) of 2 nm was analyzed. The relationship of channel length, gate length, top and bottom gate oxide layer thickness, a gate oxide material, and the rectangular wafer with upgraded structural characteristics and the parameters, such as switch current ratio (ION/IOFF) and transconductance (Gm) was analyzed for hybrid RF applications. Methods: This work was carried out at 300 K utilizing a Non-Equilibrium Green Function (NEGF) mechanism for the proposed DG MOSFET architecture with La2O3 (EOT=1 nm) as gate dielectric oxide and source-drain device length (LSD) of 45 nm. It resulted in a maximum drain current (IDmax) of 4.52 mA, where the drain-source voltage (VDS) varied between 0 V and 0.5 V at the fixed gate to source voltage (VGS) = 0.5V. The ON current(ION), leakage current (IOFF), and (ION/IOFF) switching current ratios of 1.56 mA, 8.4910-6 μA, and 18.3107 µA were obtained when the gate to source voltage (VGS) varied between 0 and 0.5V at fixed drain-source voltage (VDS)=0.5V. Results: The simulated result showed the values of maximum current density (Jmax), one and two-dimensional electron density (N1D and N2D), electron mobility (µn), transconductance (Gm), and Subthreshold Slope (SS) are 52.4 µA/m2, 3.6107 cm-1, 11.361012 cm-2, 1417 cm2V-1S-1, 3140 µS/µm, and 178 mV/dec, respectively. The Fermi-Dirac statistics were employed to limit the charge distribution of holes and electrons at a semiconductor-insulator interface. The flat-band voltage (VFB) of - 0.45 V for the fixed threshold voltage greatly impacted the breakdown voltage. The results were obtained by applying carriers to the channels with the [001] axis perpendicular to the gate oxide. The sub-band energy profile and electron density were well implemented and derived using the Non-Equilibrium Green’s Function(NEGF) formalism. Further, a few advantages of the proposed heterostructure-based DG MOSFET structure over the other structures were observed. Conclusion: This proposed design, with a reduction in the leakage current characteristics, is mainly suitable for advanced Silicon-based solid-state CMOS devices, Microelectronics, Nanotechnologies, and future-generation device applications.