A Java Processor IP Design for Embedded SoC

Author:

Tsai Chun-Jen1,Kuo Han-Wen1,Lin Zigang1,Guo Zi-Jing1,Wang Jun-Fu2

Affiliation:

1. National Chiao Tung University, Hsinchu, Taiwan

2. National Chiao Tung University, Taiwan

Abstract

In this article, we present a reusable Java processor IP for application processors of embedded systems. For the Java microarchitecture, we propose a low-cost stack memory design that supports a two-fold instruction folding pipeline and a low-complexity Java exception handling hardware. We also propose a mapping between the Java dynamic class loading model and the SoC platform-based design principle so that the Java core can be encapsulated as a reusable IP. To achieve this goal, a two-level method area with two on-chip circular buffers is proposed as an interface between the RISC core and the Java core. The proposed architecture is implemented on a Xilinx Virtex-5 FPGA device. Experimental results show that its performance has some advantages over other Java processors and a Java VM with JIT acceleration on a PowerPC platform.

Funder

National Science Council of Taiwan

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

Reference44 articles.

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2. HAKMEM: MIT Artificial Intelligence Laboratory, Memo AIM-239;Beeler M.;Item,1972

3. Stack operations folding in Java processors

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3. A Hardwired Priority-Queue Scheduler for a Four-Core Java SoC;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018-05

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