Author:
Wong D. F.,Sakhamuri P. S.
Cited by
11 articles.
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1. Development of Automation Tool for Optimising Floorplan of a Given VLSI Design;2022 IEEE 19th India Council International Conference (INDICON);2022-11-24
2. Chip Planning;VLSI Physical Design: From Graph Partitioning to Timing Closure;2022
3. Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engine;Microelectronics Journal;2014-04
4. Constrained Two Dimensional Bin Packing Using a Genetic Algorithm;Recent Advances in Intelligent Paradigms and Applications;2003
5. Fast floorplanning for effective prediction and construction;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2001-04