Threats on Logic Locking-Reference-Cited by-同舟云学术

Threats on Logic Locking

Published:2019-05-13 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2019 on Great Lakes Symposium on VLSI
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Author:

Zamiri Azar Kimia¹,Mardani Kamali Hadi¹,Homayoun Houman¹,Sasan Avesta¹

Affiliation:

1. George Mason University, Fairfax, VA, USA

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3299874.3319495

Reference33 articles.

1. Preventing IC Piracy Using Reconfigurable Logic Barriers

2. A. Chakraborty etal 2018. TimingSAT: timing profile embedded SAT attack. In ICCAD. 6. 10.1145/3240765.3240857 A. Chakraborty et al. 2018. TimingSAT: timing profile embedded SAT attack. In ICCAD. 6. 10.1145/3240765.3240857

3. H. M. Kamali etal 2018. LUT-lock: A novel LUT-based logic obfuscation for FPGA-bitstream and ASIC-hardware protection. In ISVLSI. 405--410. H. M. Kamali et al. 2018. LUT-lock: A novel LUT-based logic obfuscation for FPGA-bitstream and ASIC-hardware protection. In ISVLSI. 405--410.

4. H. M. Kamali etal 2019. Full-Lock: Hard Distributions of SAT Instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks. In DAC. 6. H. M. Kamali et al. 2019. Full-Lock: Hard Distributions of SAT Instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks. In DAC. 6.

5. H. Zhou etal 2017. CycSAT: SAT-based attack on cyclic logic encryptions. In ICCAD. 49--56. H. Zhou et al. 2017. CycSAT: SAT-based attack on cyclic logic encryptions. In ICCAD. 49--56.

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