A RISC processor architecture with a versatile stack system

Abstract

Modern RISC processors mainly differ w.r.t, the organization of their register files. There are currently three different approaches: a flat register file (e.g., MIPS), fixed-size register windows (SPARC), or a stack-like organization (AM29K). This paper describes a processor architecture with a new stack system, which is tailored to the needs of executing functional languages. In order to support a fast subroutine call mechanism and efficient parameter passing, our architecture uses a system of four stacks, of which two are interchangeable.A simulation of this processor architecture shows that a selection of functional benchmark programs can be executed with less machine cycles than equivalent code-optimized C programs on a SPARC or MIPS processor.