The DASH prototype

Author:

Lenoski Daniel,Laudon James,Joe Truman,Nakahira David,Stevens Luis,Gupta Anoop,Hennessy John

Abstract

The fundamental premise behind the DASH project is that it is feasible to build large-scale shared-memory multiprocessors with hardware cache coherence. While paper studies and software simulators are useful for understanding many high-level design trade-offs, prototypes are essential to ensure that no critical details are overlooked. A prototype provides convincing evidence of the feasibility of the design allows one to accurately estimate both the hardware and the complexity cost of various features, and provides a platform for studying real workloads. A 16-processor prototype of the DASH multiprocessor has been operational for the last six months. In this paper, the hardware overhead of directory-based cache coherence in the prototype is examined. We also discuss the performance of the system, and the speedups obtained by parallel applications running on the prototype. Using a sophisticated hardware performance monitor, we characterize the effectiveness of coherent caches and the relationship between an application's reference behavior and its speedup.

Publisher

Association for Computing Machinery (ACM)

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Affinity-Based Thread and Data Mapping in Shared Memory Systems;ACM Computing Surveys;2017-12-31

2. Distance-aware L2 cache organizations for scalable multiprocessor systems;Journal of Systems Architecture;2005-06

3. A simulation applet for microcoding exercises;Proceedings of the 2004 workshop on Computer architecture education held in conjunction with the 31st International Symposium on Computer Architecture - WCAE '04;2004

4. Hierarchical loop scheduling for clustered NUMA machines;Journal of Systems and Software;2000-11

5. Classifying and alleviating the communication overheads in matrix computations on large-scale NUMA multiprocessors;Journal of Systems and Software;1998-12

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