Abstract
A simple technique is presented which allows an optimizing compiler to more precisely compare the performance of alternative instruction sequences on a complex RISC architecture so that the better sequence can be chosen. This technique may be faster than current techniques, and has the advantage that minor modifications to the hardware do not require any changes to the compiler (not even recompilation), and yet have an immediate effect on instruction scheduling decisions.
Publisher
Association for Computing Machinery (ACM)
Reference23 articles.
1. Appel Andrew. Private communication July 1991. Appel Andrew. Private communication July 1991.
2. ATT. WE® DSP32C Digital Signal Processor Advance Data Sheet. ATT Microelectronics Allentown PA May 1988. ATT. WE® DSP32C Digital Signal Processor Advance Data Sheet . ATT Microelectronics Allentown PA May 1988.
3. Baker Henry and Parker Clinton. Micro SPL. Synapse Computer Services Sept. 1979. Baker Henry and Parker Clinton. Micro SPL . Synapse Computer Services Sept. 1979.
4. Baker Henry and Parker Clinton. "High Level Language Programs Run Ten Times Faster in Microstore". Tech. Rept. Synapse Computer Services 1980. Baker Henry and Parker Clinton. "High Level Language Programs Run Ten Times Faster in Microstore". Tech. Rept. Synapse Computer Services 1980.
5. The Marion system for retargetable instruction scheduling
Cited by
6 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献