Tuning architecture at run-time

Abstract

We describe the structure and operational mode of a coprocessor system which, when incorporated in a microprogrammed syetem to carry out Dynamic Vertical Migration, improves execution speed for any program. The coprocessor includes an interconnection mechanism between the machine code and the instruction set microcode. The interconnections (Intermediate instructions) are created in parallel with machine instruction execution and so do not increase normal execution time. This intermediate code is stored dynamically in coprocessor memory, saving the fetching and decoding phases in subsequent executions, speeding up the execution of repetitive machine code.The coprocessor structure is organized around three basic elements: Interconnection Memory, Interconnection Memory Management Unit and Coprocessor Control Unit. A software simulator has been developed to analyse coprocessor behaviour and a theoretical model has been formulated from the results ot these analyses.