Fast Miss Ratio Curve Modeling for Storage Cache

Author:

Hu Xiameng1,Wang Xiaolin1,Zhou Lan1,Luo Yingwei2,Wang Zhenlin3,Ding Chen4,Ye Chencheng5

Affiliation:

1. Peking University, Beijing, P.R.China

2. Peking University; Shenzhen Key Lab for Cloud Computing Technology 8 Applications, SECE, Peking University, SHENZHEN

3. Michigan Technological University, Townsend Drive, Houghton, MI

4. University of Rochester, Rochester, NY

5. Huazhong University of Science and Technology, Wuhan, P.R.China

Abstract

The reuse distance (least recently used (LRU) stack distance) is an essential metric for performance prediction and optimization of storage cache. Over the past four decades, there have been steady improvements in the algorithmic efficiency of reuse distance measurement. This progress is accelerating in recent years, both in theory and practical implementation. In this article, we present a kinetic model of LRU cache memory, based on the average eviction time (AET) of the cached data. The AET model enables fast measurement and use of low-cost sampling. It can produce the miss ratio curve in linear time with extremely low space costs. On storage trace benchmarks, AET reduces the time and space costs compared to former techniques. Furthermore, AET is a composable model that can characterize shared cache behavior through sampling and modeling individual programs or traces.

Funder

National Science Foundation

IBM CAS Faculty Fellowship

National Science Foundation of China

Shenzhen Key Research

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture

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