Leveraging Hardware Transactional Memory for Cache Side-Channel Defenses-Reference-Cited by-同舟云学术

Leveraging Hardware Transactional Memory for Cache Side-Channel Defenses

Published:2018-05-29 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2018 on Asia Conference on Computer and Communications Security
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Author:

Chen Sanchuan¹,Liu Fangfei²,Mi Zeyu³,Zhang Yinqian¹,Lee Ruby B.⁴,Chen Haibo³,Wang XiaoFeng⁵

Affiliation:

1. Ohio State University, Columbus, OH, USA

2. Intel Corporation, Hillsboro, OR, USA

3. Shanghai Jiao Tong University, Shanghai, China

4. Princeton University, Princeton, NJ, USA

5. Indiana University at Bloomington, Bloomington, IN, USA

Funder

National Science Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3196494.3196501

Reference15 articles.

1. Gorka Irazoqui Apecechea Mehmet Sinan Inci Thomas Eisenbarth and Berk Sunar. 2014. Fine grain Cross-VM attacks on Xen and VMware are possible! Cryptology ePrint Archive. Gorka Irazoqui Apecechea Mehmet Sinan Inci Thomas Eisenbarth and Berk Sunar. 2014. Fine grain Cross-VM attacks on Xen and VMware are possible! Cryptology ePrint Archive.

2. Daniel J. Bernstein. 200

3. Cache-Collision Timing Attacks Against AES

4. Intel Corporation. 2014. Intel 64 and IA-32 Architectures Software Developer's Manual Combined Volumes: 1 2A 2B 2C 3A 3B and 3C. (2014). Intel Corporation. 2014. Intel 64 and IA-32 Architectures Software Developer's Manual Combined Volumes: 1 2A 2B 2C 3A 3B and 3C. (2014).

5. Stephen Crane Andrei Homescu Stefan Brunthaler Per Larsen and Michael Franz. 2015. Thwarting cache side-channel attacks through dynamic software diversity ISOC Network and Distributed System Security Symposium. Stephen Crane Andrei Homescu Stefan Brunthaler Per Larsen and Michael Franz. 2015. Thwarting cache side-channel attacks through dynamic software diversity ISOC Network and Distributed System Security Symposium.

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