Affiliation:
1. Brown University, Division of Engineering
2. Compaq Computer Corporation, VSSAD/Alpha Development Group
Abstract
Minimizing power dissipation is an important design requirement for both portable and non-portable systems. In this work, we propose an architectural solution to the power problem that retains performance while reducing power. The technique, known as
Pipeline Balancing (PLB),
dynamically tunes the resources of a general purpose processor to the needs of the program by monitoring performance within each program. We analyze metrics for triggering
PLB,
and detail instruction queue design and energy savings based on an extension of the Alpha 21264 processor. Using a detailed simulator, we present component and full chip power and energy savings for single and multi-threaded execution. Results show an issue queue and execution unit power reduction of up to 23% and 13%, respectively, with an average performance loss of 1% to 2%
.
Publisher
Association for Computing Machinery (ACM)
Reference18 articles.
1. V. Arasanipalai. Private communication Compaq Computer Corporation. V. Arasanipalai. Private communication Compaq Computer Corporation.
Cited by
4 articles.
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