1. Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory Layout;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-05
2. Data-aware process networks;Proceedings of the 30th ACM SIGPLAN International Conference on Compiler Construction;2021-02-27
3. Background;Separation Logic for High-level Synthesis;2017
4. FPGA Synthesis and Physical Design;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14
5. MATCHUP;Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2015-02-22