Declarative Language for Geometric Pattern Matching in VLSI Process Rule Modeling-Reference-Cited by-同舟云学术

Declarative Language for Geometric Pattern Matching in VLSI Process Rule Modeling

Published:2019-04-04 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2019 International Symposium on Physical Design
language:
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Author:

Suto Gyuszi¹,Greenleaf Geoff S.¹,Bhagavatula Phanindra²,Fischer Heinrich R.¹,Soni Sanjay K.¹,Miller Brian H.¹,Hentschke Renato F.¹

Affiliation:

1. Intel Corporation, Hillsboro, OR, USA

2. Intel Corporation, Santa Clara, CA, USA

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3299902.3309745

Reference7 articles.

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3. Alexander Nadel . Bit-vector rewriting with automatic rule generation. In Armin Biere and Roderick Bloem editors Computer Aided Verification -- 26th International Conference CAV 2014 Held as Part of the Vienna Summer of Logic VSL 2014 (Vienna Austria July 18-22 2014). Proceedings volume 8559 of Lecture Notes in Computer Science pages 663 -- 679 . Springer 2014. 10.1007/978-3-319-08867-9_44 Alexander Nadel. Bit-vector rewriting with automatic rule generation. In Armin Biere and Roderick Bloem editors Computer Aided Verification -- 26th International Conference CAV 2014 Held as Part of the Vienna Summer of Logic VSL 2014 (Vienna Austria July 18-22 2014). Proceedings volume 8559 of Lecture Notes in Computer Science pages 663--679. Springer 2014. 10.1007/978-3-319-08867-9_44

4. Boost Polygon DOI=https://www.boost.org/doc/libs/1_68_0/libs/polygon/doc/index.htm Boost Polygon DOI=https://www.boost.org/doc/libs/1_68_0/libs/polygon/doc/index.htm

5. Graphviz Linux DOI=https://graphviz.gitlab.io/documentation/ Graphviz Linux DOI=https://graphviz.gitlab.io/documentation/