A compiler cost model for speculative parallelization

Author:

Dou Jialin1,Cintra Marcelo2

Affiliation:

1. ARM Ltd., Cambridge, UK

2. University of Edinburgh, Edinburgh, United Kingdom

Abstract

Speculative parallelization is a technique that allows code sections that cannot be fully analyzed by the compiler to be aggressively executed in parallel. However, while speculative parallelization can potentially deliver significant speedups, several overheads associated with this technique can limit these speedups in practice. This paper proposes a novel compiler static cost model of speculative multithreaded execution that can be used to predict the resulting performance. This model attempts to predict the expected speedups, or slowdowns, of the candidate speculative sections based on the estimation of the combined runtime effects of various overheads, and taking into account the scheduling restrictions of most speculative execution environments. The model is based on estimating the likely execution duration of threads and considers all the possible permutations of these threads. This model also produces a quantitative estimate of the speedup, which is different from prior heuristics that only qualitatively estimate the benefits of speculative multithreaded execution. In previous work, a limited version of the framework was evaluated on a number of loops from a collection of SPEC benchmarks that suffer mainly from load imbalance and thread dispatch and commit overheads. In this work, an extended framework is also evaluated on loops that may suffer from data-dependence violations. Experimental results show that prediction accuracy is lower when loops with violations are included. Nevertheless, accuracy is still very high for a static model: the framework can identify, on average, 45% of the loops that cause slowdowns and, on average, 96% of the loops that lead to speedups; it predicts the speedups or slowdowns with an error of less than 20% for an average of 28% of the loops across the benchmarks and with an error of less than 50% for an average of 80% of the loops. Overall, the framework often outperforms, by as much as 25%, a naive approach that attempts to speculatively parallelize all the loops considered, and is able to curb the large slowdowns caused in many cases by this naive approach.

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Information Systems,Software

Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. APT-GET;Proceedings of the Seventeenth European Conference on Computer Systems;2022-03-28

2. A cost model for a graph-based intermediate-representation in a dynamic compiler;Proceedings of the 10th ACM SIGPLAN International Workshop on Virtual Machines and Intermediate Languages;2018-11-04

3. A Survey on Thread-Level Speculation Techniques;ACM Computing Surveys;2016-11-11

4. Exhaustive analysis of thread-level speculation;Proceedings of the 3rd International Workshop on Software Engineering for Parallel Systems;2016-10-21

5. Dynamic Core Allocation for Energy-Efficient Thread-Level Speculation;2014 IEEE 17th International Conference on Computational Science and Engineering;2014-12

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