The P4->NetFPGA Workflow for Line-Rate Packet Processing
Author:
Affiliation:
1. Stanford University, Stanford, CA, USA
2. Xilinx Labs, San Jose, CA, USA
3. University of Cambridge, Cambridge, United Kingdom
Funder
The Leverhulme Trust
Isaac Newton Trust
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3289602.3293924
Reference38 articles.
1. P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers
2. ONOS
3. Philippe Biondi. 2018. Scapy. https://scapy.net/ Philippe Biondi. 2018. Scapy. https://scapy.net/
4. P4
5. High-Speed Packet Processing using Reconfigurable Computing
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