A dynamic assertion-based verification platform for validation of UML designs

Abstract

Capacity limitations continue to impede widespread adoption of formal property verification in the design validation ow of software and hardware systems. The more popular choice (at least in the hardware domain) has been dynamic property verification (DPV), which is a semi-formal approach where the formal properties are checked over simulation runs. DPV is highly scalable and can support a rich specification language. The main contribution of this paper is to build an integrated DPV platform for validation of UML-based designs. Specifically, we present (a) a language, named Action-LTL (a simple extension of Linear Temporal Logic) for writing assertions over data attributes and events of UML models, and (b) an integrated dynamic assertion-verification platform for verification of UML designs. In view of the capacity limitations of existing formal property verification tools, we believe that the methods presented in this paper are of immediate practical value to the UML design community.