Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects-Reference-Cited by-同舟云学术

Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects

Published:2024-03-12 Issue: Volume:9 Page:85-90
ISSN:
Container-title:Proceedings of the 2024 International Symposium on Physical Design
language:
Short-container-title:

Author:

Choy Jun-Ho¹^ORCID,Moreau Stéphane²^ORCID,Brunet-Manquat Catherine²^ORCID,Sukharev Valeriy¹^ORCID,Kteyan Armen³^ORCID

Affiliation:

1. D2S, Siemens EDA, Fremont, CA, USA

2. Univ. Grenoble Alpes, CEA, Leti, Grenoble, France

3. D2S, Siemens EDA, Yerevan, Armenia

Funder

French National Research Agency (ANR)

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3626184.3635284

Reference12 articles.

1. V. Sukharev, A. Kteyan, J. Choy, "An accurate assessment of Chip-Package Interaction is a key factor for designing resilient 3D IC systems", International 3D Systems Integration Conference (3DIC), Sendai, Japan, (2019).

2. Advanced methodology for assessing chip package interaction effects on chip performance and reliability after chip assembly and during chip operation

3. A. Kteyan, J. Choy, V. Sukharev, M. Bertoletti, C. Maiorca, R. Zadra, M. Inzaghi, G. Gattere, G. Zinco, P. Valente, R. Bardelli, A. Valerio, P. Rolandi, M. Monett, V. Cuomo, S. Santapà, "Novel Methodology for Assessing Chip-Package Interaction Effects on Chip Performance", Proc. International Symposium on Physical Design, March 27--30, Virtual Event Canada, (2022).

4. The quest of porous ELK materials for high performance logic technologies

5. W. Chen, B, Sammakia, I. Qin, J. Wilcox, E. Cotts, A. Teng, S. Rangarajan, M. Gerber, K. Erickson, V. Sukharev, L. Shan, B. Chan, K. Lee, P. Ho, Ch.8. Single and Multichip integration, Heterogeneous Integration Roadmap, ed. by P. Wesling, IEEE (2021).