Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates Insertion
Author:
Affiliation:
1. Southeast University, Nanjing, China
2. Beijing University of Posts and Telecommunications, Beijing, China
Funder
National Natural Science Foundation of China
National 863 Program
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3194554.3194600
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5. A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation
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1. TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2020-05
2. A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System;IEEE Journal of Solid-State Circuits;2020-03
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