Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates Insertion-Reference-Cited by-同舟云学术

Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates Insertion

Published:2018-05-30 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2018 on Great Lakes Symposium on VLSI
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Author:

Dai Wentao¹,Liu Peiye²,Shan Weiwei¹

Affiliation:

1. Southeast University, Nanjing, China

2. Beijing University of Posts and Telecommunications, Beijing, China

Funder

National Natural Science Foundation of China

National 863 Program

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3194554.3194600

Reference17 articles.

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4. D. Ernst etal "Razor: A low-power pipeline based on circuitlevel timing speculation " in MICRO 2003. D. Ernst et al. "Razor: A low-power pipeline based on circuitlevel timing speculation " in MICRO 2003.

5. A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation

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