Optimal VLSI architectures for multidimensional DFT (preliminary version)

Abstract

A family of VLSI architectures for computing an ( n 1 × n 2 × … × n d )-point multidimensional DFT (MDDFT) over ℤ M , the ring of integers modulo M , is presented. These architectures achieve VLSI area A = O (( N 2 log 2 M )/ T 2 for any computation time T ∊ [Ω(log N ), O (√ N log M )] where N = ∏ d k =1 n k and it is assumed that log M = O (log N ). A lower bound argument is developed to show that the proposed architectures are area-time optimal. The applicability of these architectures to computation of the MDDFT over the complex field is also discussed. Using fixed-point arithmetic with b bits of precision, their area-time performance is AT 2 = O ( N 2 b 2 ) for any computation time T ∊ [Ω(log N ), O (√ Nb )].