Hot-LSNs distributing wear-leveling algorithm for flash memory

Abstract

Flash memory offers attractive features, such as non-volatile, shock resistance, fast access and low power consumption for data storage. However, it has one main drawback of requiring an erase before updating the contents. Furthermore, the flash memory can only be erased for a limited number of times. These characteristics are controlled by a software layer called the flash translation layer (FTL). FTL efficiently manages read, write, and erase operations to enhance the overall performance, and considers wear-leveling to prolong the durability of flash memory. In this article, we identify the logical sector numbers corresponding to random data, termed as hot-LSNs, and distribute them to all available blocks without degrading the performance of the flash memory. From our evaluation, we found that the extra erase operations for distributing the hot-LSNs are very low compared to the overall performance. Even though Hot-LSNs Distributing Wear-Leveling Algorithm (Hot-DL) incorporates wear-leveling in the performance enhancing algorithm, Hot-DL only requires approximately 0.015% of extra erase operations compared to previous well-optimized performance enhancing algorithms, shared buffer scheme.